Field-programmable gate array

• 1. Introduction

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  A field-programmable gate array, or FPGA, is a circuit that you can rewrite after it leaves the factory. Most chips are fixed at the moment they are made. An FPGA is different: its internal logic can be rearranged again and again, in the field, long after manufacturing is done. That single property has made FPGAs indispensable everywhere from military radios to cloud data centers to medical imaging machines. How does a reprogrammable chip actually work? Who built the first one, and why did it take nearly three decades to grow from a niche curiosity into a market worth billions of dollars? And what happens when the flexibility that makes FPGAs so useful also opens the door to serious security vulnerabilities?

• 2. Origins and Early Rivals

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  Altera was founded in 1983 and delivered what it called the industry's first reprogrammable logic device the following year, the EP300. That device contained a quartz window in its packaging so users could shine an ultraviolet lamp on the die and erase the memory cells holding its configuration. The erasure method was cumbersome, but the concept was radical.

  Xilinx moved faster toward a practical solution. In 1985 the company produced the XC2064, the first commercially viable field-programmable gate array. The XC2064 carried 64 configurable logic blocks, each with two three-input lookup tables. Those lookup tables, known as LUTs, became the foundational unit of FPGA design.

  For roughly a decade, Altera and Xilinx grew unchallenged. By 1993, however, a company called Actel, later renamed Microsemi and eventually absorbed by Microchip, had captured about 18 percent of the FPGA market. Competition had arrived, and it would only intensify from there.

  The market that these rivals were contesting grew fast. In 1987 the total FPGA market was worth approximately 14 million dollars. By 1993 it had surpassed 385 million dollars. By 2005 it reached 1.9 billion dollars, and by 2013 it stood at 5.4 billion dollars, with projections placing it near 23 billion dollars by 2030.

• 3. How FPGAs Are Built

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  Inside an FPGA, the fundamental unit of computation is the configurable logic block, called a CLB or, depending on the manufacturer, a logic array block. A typical cell within one of these blocks contains a four-input lookup table, a full adder, and a D-type flip-flop. The LUT can itself be split into two three-input LUTs, and the selection between arithmetic and normal mode is programmed into a multiplexer.

  These logic blocks sit within a grid of routing channels. The channels carry signals between blocks, and their width, measured in the number of signals they carry, is generally uniform across the chip. Manufacturers try to supply just enough routing channels so that most designs fitting the available LUTs and input/output pins can also be routed, using estimation techniques such as Rent's rule.

  Modern FPGAs go far beyond bare logic. Higher-end families embed hard blocks fixed in silicon: multipliers, digital signal processing blocks, embedded processors, and multi-gigabit transceivers capable of operating at 28 Gbit/s. These hard blocks sit alongside the programmable fabric but are built from transistors rather than LUTs, giving them performance and power consumption comparable to fixed-function chips. Higher-level functions such as PCI Express controllers, Ethernet units, and external memory controllers can all be embedded this way.

  Some mixed-signal FPGAs go further still, integrating analog-to-digital and digital-to-analog converters alongside analog signal conditioning. A device of this type blurs the boundary between an FPGA and what engineers call a field-programmable analog array, or FPAA.

• 4. Programming the Fabric

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  Defining what an FPGA does requires writing in a hardware description language. The two dominant languages are VHDL and Verilog. VHDL is based on the Ada programming language, while Verilog was designed later with a C-like syntax to make HDL more flexible and approachable. National Instruments' LabVIEW graphical language also offers an FPGA add-in module for engineers who prefer a visual workflow.

  From the HDL source, an electronic design automation tool generates a technology-mapped netlist, which is then fitted to the physical chip through a process called place and route. After timing analysis and simulation confirm the design works correctly, a binary configuration file is transferred to the chip, typically through a serial interface called JTAG or through an external EEPROM.

  The dominant programming technology is SRAM-based. SRAM chips are in-system programmable and re-programmable, but they are volatile: the chip loses its configuration when power is cut and must reload from an external flash or EEPROM device on every startup. Alternatives exist for applications where that is unacceptable. Antifuse devices, such as the Actel SX and Axcelerator families, are one-time programmable and highly resistant to tampering. Flash-based devices, such as the Actel ProASIC family, can be erased in the field without ultraviolet light and can store their configuration internally without an external boot memory.

  For complex system designs, pre-built circuits called intellectual property cores, or IP cores, shorten development time. Those from vendor catalogs are rarely free and typically sold under proprietary licenses. Open alternatives come from communities such as OpenCores, released under licenses like the GPL or BSD, forming what the industry calls open-source hardware.

• 5. From Defense Labs to Data Centers

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  In 1987, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman. The goal was to build a computer implementing 600,000 reprogrammable gates. Casselman succeeded, and a patent on the system was issued in 1992. That experiment pushed gate counts far beyond what commercial products had achieved, demonstrating that FPGAs could serve as the basis for serious computation.

  Through the 1990s, the primary customers were telecommunications and networking companies. By the end of that decade the technology spread into consumer electronics, automotive products, and industrial systems. The introduction of dedicated multipliers into FPGA architectures in the late 1990s pulled FPGAs into territory that had been the exclusive domain of digital signal processors.

  Microsoft became one of the most visible corporate adopters. In 2014 the company began using FPGAs to accelerate the Bing search engine, drawn by the performance-per-watt advantage the chips offer. By 2018, Microsoft was deploying FPGAs across other workloads inside its Azure cloud computing platform. The military found its own reasons: FPGAs power the Joint Tactical Radio System used by the US military, providing adaptable, real-time signal processing across multiple communication standards and encryption methods.

  In 2012, Xilinx introduced its 28-nanometer 7-series FPGAs using a stacked-die architecture. Several high-density parts in that line were constructed by placing multiple active FPGA dies side by side on a silicon interposer, a passive piece of silicon that carries the interconnect between them. This approach allowed different parts of the chip to be manufactured using different process technologies, which matters because the fabric itself and the high-speed 28 Gbit/s serial transceivers have very different fabrication requirements. The result is called a heterogeneous FPGA.

• 6. Security and Vulnerabilities

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  In 2012, researchers Sergei Skorobogatov and Christopher Woods published a finding that alarmed the FPGA community. They demonstrated a critical backdoor vulnerability built into silicon inside the Actel/Microsemi ProAsic 3 device. That backdoor could be used to reprogram cryptographic and access keys, extract unencrypted configuration data, and modify low-level silicon features.

  Eight years later, in 2020, a separate vulnerability named Starbleed was discovered across all Xilinx 7-series FPGAs. The flaw rendered bitstream encryption useless. Xilinx confirmed the problem but produced no hardware revision. Ultrascale and later devices, which were already shipping at the time, were not affected.

  The industry has developed countermeasures. Altera and Xilinx both offer AES encryption of up to 256 bits for bitstreams stored in external flash. A technology called a physical unclonable function, or PUF, uses the unique electrical signature of each individual chip to authenticate it, and PUFs can be integrated into FPGAs while consuming very little hardware area. With its Stratix 10 product line, Altera introduced a dedicated Secure Device Manager alongside PUF support to protect against physical attacks.

  FPGAs that store their configuration in internal nonvolatile flash, such as Microsemi's ProAsic 3 or Lattice's XP2, avoid one vulnerability entirely: the bitstream is never exposed on an external bus during startup. For applications demanding the highest tamper resistance, write-once antifuse FPGAs from vendors such as Microsemi remain an option.

• 7. Consolidation at the Top

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  By 2013, Xilinx held 36 percent of the FPGA market, Altera held 31 percent, and Actel held 10 percent. Together those three companies controlled roughly 77 percent of the market. The remaining share was split among a range of smaller players: Achronix with SRAM-based fabric running at 1.5 GHz, Lattice Semiconductor targeting low-power applications, GOWIN Semiconductors offering pin-compatible replacements for some Xilinx, Altera, and Lattice products, and QuickLogic focusing on ultra-low-power sensor applications.

  On June the 1st, 2015, Intel announced it would acquire Altera for approximately 16.7 billion dollars. The deal closed on December the 30th of that year. Five years later, on October the 27th, 2020, AMD announced it would acquire Xilinx in a transaction ultimately valued at about 50 billion dollars, which completed in February 2022. Within the span of a decade, both of the industry's founding companies had been absorbed by processor manufacturers.

  The acquisitions reflected a strategic calculation: general-purpose processors and FPGAs had become deeply complementary in the data center and AI markets. Since 2019, modern FPGA generations have been integrated with AI engine architectures to target machine learning workloads directly. In February 2024, Altera once again became independent of Intel, reopening the question of how the two halves of the computing industry will relate to each other.