Application-specific integrated circuit

• 1. Introduction

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  An application-specific integrated circuit, or ASIC, is a chip built for exactly one job. Not a general-purpose processor. Not a flexible platform. One job. That single-minded focus has made ASICs the invisible backbone of modern electronics, from digital voice recorders to high-efficiency video codecs. But the road from concept to physical silicon is anything but simple. How do engineers take an idea and carve it into a chip that cannot be changed once it leaves the factory? And how did a technology born in gate arrays and bipolar logic evolve into the system-on-chip designs that now pack entire microprocessors, RAM, ROM, flash memory, and more onto a single die? Those are the questions this documentary will answer.

• 2. Origins in Gate Arrays

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  By 1967, two companies had already staked out the earliest ground in ASIC history: Ferranti and Interdesign were manufacturing bipolar gate arrays that year. That same year, Fairchild Semiconductor introduced its Micromatrix family, covering both diode-transistor logic and transistor-transistor logic arrays. These were the raw first steps toward customizable silicon.

  The real commercial opening came with a different material. Complementary metal-oxide-semiconductor technology, known as CMOS, made gate arrays practical for a far wider market. Robert Lipp developed the first CMOS gate arrays in 1974 for a company called International Microcircuits, Inc. That work cracked open a door that manufacturers rushed through in the years following.

  Metal-oxide-semiconductor standard-cell technology arrived in the 1970s under two trade names: Micromosaic, from Fairchild, and Polycell, from Motorola. VLSI Technology, founded in 1979, and LSI Logic, which followed in 1981, were the companies that turned those ideas into commercial success.

  One early proof that gate arrays could serve mass-market products came from the United Kingdom. Sinclair Research used gate array circuitry as a low-cost input/output solution in two personal computers: the 8-bit ZX81, introduced in 1981, and the ZX Spectrum, which followed in 1982. The company was primarily solving one practical problem: handling the computers' graphics at minimal expense. Those two machines demonstrated that specialized silicon did not have to be exotic or expensive.

• 3. Standard-Cell Design Matures

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  In the mid-1980s, ASIC designers faced a practical bottleneck. Each manufacturer offered its own design tools, and third-party tools had no reliable connection to the actual electrical characteristics of a given factory's process. Most designers had little choice but to use the factory's own software to complete their work.

  Standard cells were the solution. By defining functional blocks with known electrical properties, including propagation delay, capacitance, and inductance, manufacturers gave designers a shared vocabulary. Those blocks could be represented in third-party tools, which finally broke the factory lock-in. Standard-cell design produced higher gate density and better electrical performance than gate arrays had managed.

  By the late 1990s, logic synthesis tools added another layer of automation. These tools could compile a description written in a hardware description language, such as Verilog or VHDL, directly into a gate-level netlist. The design flow that emerged has several overlapping stages: requirements engineering, register-transfer level design, functional verification, logic synthesis, placement, routing, and finally sign-off. Each stage feeds into the next, though in practice the boundaries blur.

  Sign-off is worth pausing on. Once a layout is final, circuit extraction computes the parasitic resistances and capacitances hiding in the physical structure. Static timing analysis uses that data to estimate actual circuit performance. Design rule checking and power analysis run in parallel. Only when all of those tests pass is the photomask information released to the fabrication facility. Because ASICs, unlike most field-programmable gate arrays, cannot be reprogrammed after manufacture, a flaw caught at sign-off is far cheaper than one discovered in silicon.

• 4. Choosing the Right Design Style

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  Gate-array design defined one pole of the ASIC world for decades. In gate-array manufacturing, the diffused layers of transistors and active devices are pre-built and held in stock, unconnected, until an order arrives. Customization happens only at the metallization stage, which requires photomasks for as few as two to nine metal layers rather than for a full mask set. That makes non-recurring engineering costs significantly lower, and production cycles much shorter, than full-custom approaches.

  The trade-off is efficiency. Mapping any given design onto a stock wafer never achieves 100 percent circuit utilization. Routing difficulties sometimes force a move to a larger array device, pushing up the unit price. Pure logic-only gate-array design has largely disappeared from modern practice, replaced by field-programmable gate arrays that the user can configure without any tooling charges at all.

  Full-custom design sits at the opposite extreme. It defines every photolithographic layer from scratch. The benefits include smaller die area, lower recurring component cost, better performance, and the ability to integrate analog components alongside digital logic. The costs are steep: longer design and manufacturing timelines, higher non-recurring engineering expenses, more demanding electronic design automation systems, and a significantly higher skill requirement from the design team.

  For digital-only work, standard-cell libraries with modern computer-aided design systems offer a middle path. Automated layout tools handle most of the work quickly, while still allowing designers to manually optimize performance-critical sections. Non-recurring engineering costs for ASICs in general can run into the millions of dollars, which is why manufacturers tend to reserve ASIC designs for very large production volumes, where that upfront cost spreads across many units.

• 5. Structured ASICs and the New Middle Ground

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  Structured ASIC design, sometimes called platform ASIC design, emerged as a relatively new trend aimed at cutting both manufacturing cycle time and design cycle time compared to traditional cell-based approaches. The Foundations of Embedded Systems definition captures the core idea: the logic mask-layers of the device are predefined by the ASIC vendor, and customization happens only through metal layers that connect those predefined lower-layer elements.

  What separates structured ASICs from older gate arrays is the purpose of the predefined metallization. In a gate array, pre-defined metal layers exist mainly to speed up manufacturing turnaround. In a structured ASIC, the goal is primarily to reduce the cost of mask sets and shorten design cycle time. That distinction matters for how a design team budgets both money and schedule.

  Structured ASICs also shift which tasks fall to the designer. Power structures, clock distribution, and test structures are often predefined by the vendor, saving the team work that a gate-array project would leave entirely to them. The design tools for structured ASICs tend to be lower in cost and faster to use than full cell-based tools, because they do not need to perform every function that cell-based tools require. Some vendors do require their own customized physical synthesis tools, which has the side effect of accelerating the path to manufacturing.

  Today, gate arrays are evolving toward structured ASICs that carry large IP cores, digital signal processor units, peripherals, standard interfaces, integrated memories, SRAM, and reconfigurable logic all on the same device, reflecting the broader shift toward systems on a chip that need far more than simple functional units.

• 6. IP Cores and the Ecosystem of Reuse

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  Cell libraries of logical primitives are generally provided by the device manufacturer as part of the service, covered by a non-disclosure agreement and treated as intellectual property. Because their physical design is pre-defined, they are classed as hard macros: fixed, verified blocks that drop directly into a layout.

  The broader market for intellectual property centers on IP cores, which are designs purchased from third parties and embedded as sub-components in a larger ASIC. Cores arrive in two forms. A soft macro is delivered as a hardware description language description, making it largely process-independent. It can be fabricated on a wide range of manufacturing processes and by different manufacturers. A hard macro is a fully routed design that can be printed directly onto an ASIC mask, but it is process-limited and usually requires additional design effort to migrate to a different process or manufacturer.

  The catalog of available cores is broad. Many organizations sell pre-designed CPU cores, Ethernet interfaces, USB interfaces, and telephone interfaces. Larger organizations may dedicate an entire department to producing cores for internal use across other divisions. The company ARM operates exclusively in this space: it sells only IP cores, making it a fabless manufacturer with no fabrication facilities of its own.

  Open-source hardware has entered this space as well. Organizations such as OpenCores collect free IP cores, running a direct parallel to the open-source software movement in the hardware domain. The argument for reuse is straightforward: a core takes a great deal of time and investment to create. Once it exists, reusing and refining it cuts product cycle times sharply and tends to produce better products than starting from scratch.

• 7. From Prototypes to Production

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  Multi-project wafer services, often called shuttles or MPWs, exist specifically to make low-cost prototyping accessible. Several designs share a single wafer run, with each project contributing to the cost. These runs take place at regular scheduled intervals on a cut-and-go basis, typically with limited liability on the manufacturer's side. The output is either bare dies or a small assembled and packaged batch of devices.

  The service requires the designer to supply a physical design database, meaning the masking information or pattern generation tape. The manufacturer in this context is often called a silicon foundry, a term that signals its limited involvement in the design itself. The foundry provides fabrication capacity; the design team provides everything else.

  The maximum complexity that an ASIC can achieve has expanded enormously as feature sizes have shrunk and design tools have improved. Early designs topped out at around 5,000 logic gates. Modern ASICs routinely exceed 100 million logic gates. That growth in capacity is what made systems on a chip, or SoCs, possible: devices that integrate entire microprocessors, ROM, RAM, EEPROM, flash memory, and other large functional blocks on a single die.

  Application-specific standard products, or ASSPs, represent a related but distinct category. An ASSP implements a specific function that appeals to a wide market, rather than being designed for a single customer. Ethernet network interface controller chips and flash memory controller chips are practical examples. A controller chip for a PC or a chip for a modem sits in an ambiguous zone: both are application-specific in function, but both are sold to many different system vendors, which is the defining characteristic of a standard product rather than a custom one.