Random-access memory
In June of 1948, the Manchester Baby computer successfully ran its first program. This machine relied on a Williams tube for its main memory. The Williams tube stored data as electrically charged spots on the face of a cathode-ray tube. An electron beam could read and write these spots in any order. This capability made it true random-access memory. Earlier computers used relays or mechanical counters to store information. Ultrasonic delay lines were serial devices that reproduced data only in the order written. Drum memory offered low-cost expansion but required knowledge of physical layout for efficient retrieval. Latches built from triode vacuum tubes served smaller memories like registers. These latches were large and costly. A system might hold only a few dozen bits using such technology. The Williams tube provided a medium much faster than individual vacuum tube latches. It held between a few hundred and around one thousand bits. Developed at the University of Manchester in England, this device enabled the first electronically stored program.
Magnetic-core memory appeared in 1947 and dominated until the mid-1970s. Engineers constructed arrays of magnetized rings to store data. Each ring represented a single bit through its direction of magnetization. Address wires selected specific rings for reading or writing operations. Any location became accessible in any sequence without mechanical delays. This standard form of computer memory persisted for decades. Semiconductor memory eventually displaced magnetic core during the early 1970s. Prior to integrated circuits, permanent random access often used diode matrices driven by address decoders. Specially wound core rope planes also stored fixed data. Magnetic cores remained the primary choice despite emerging alternatives. Their reliability and non-volatile nature made them ideal for critical systems. The transition away from these rings marked a significant shift in hardware design philosophy. By the late 1960s, new technologies began challenging their dominance. The cost advantage of semiconductors would soon prove decisive.
John Schmidt developed MOS semiconductor memory at Fairchild Semiconductor in 1964. This technology consumed less power than magnetic core while offering higher speeds. Federico Faggin created silicon-gate MOS integrated circuit technology in 1968. These innovations enabled mass production of memory chips. IBM introduced the SP95 SRAM chip in 1965 for the System/360 Model 95. Toshiba utilized bipolar DRAM cells in its Toscal BC-1411 calculator that same year. Robert Dennard invented modern DRAM architecture in 1966 with a single transistor per capacitor. Intel released the first commercial DRAM IC chip, the 1103, in October 1970. This chip held one kilobit of data on an eight-micrometer process. Bipolar DRAM offered speed but could not match the lower price of magnetic cores. MOS memory overtook magnetic core as the dominant technology by the early 1970s. Commercial use of SRAM began shortly after the initial SP95 release. The shift from discrete components to integrated circuits changed computing forever.
Static RAM uses six transistors to store each bit of data. This flip-flop circuit requires low power when inactive but remains expensive. Dynamic RAM relies on a single transistor paired with a capacitor. Charging or discharging this capacitor represents binary values. The charge leaks slowly and must refresh every few milliseconds. DRAM achieves greater storage density at lower unit costs compared to SRAM. Both types remain volatile as their state vanishes without power. SRAM serves as cache memory for CPUs due to its speed. DRAM dominates main memory systems because it is cheaper to produce. A typical computer contains both forms working together. The memory cell acts as the fundamental building block for all systems. It stores logic high voltage levels or low voltage levels until reset. Accessing these cells involves multiplexing and demultiplexing circuitry within the device. Most devices hold capacity as powers of two for addressing efficiency.
Samsung released the KM48SL2000 chip in 1992 with sixteen megabits of capacity. This synchronous dynamic random-access memory returned to synchronized operation after asynchronous designs dominated the mid-1970s. Early DRAM often synchronized directly with CPU clocks for microprocessors. The first commercial double data rate SDRAM arrived in June 1998 from Samsung. It held sixty-four megabits of data. Graphics DDR emerged as a form of synchronous graphics RAM also released by Samsung in 1998. These chips utilized sixteen megabits initially before scaling up. Modern systems rely on these evolved standards for performance. As clock frequencies rose, latency became an increasing bottleneck. The gap between processor speed and memory response time widened significantly. From 1986 to 2000, CPU speeds improved fifty-five percent annually while off-chip memory lagged at ten percent. Single-lane DDR5 modules now reach eight thousand megahertz capable of one hundred twenty-eight gigabytes per second. Fast non-volatile solid state drives have closed some gaps but remain orders of magnitude slower than RAM.
Computer systems utilize processor registers alongside on-die SRAM caches. External caches and DRAM form layers within this hierarchy. Memory paging systems extend physical limits using virtual memory or swap space on SSDs. The goal remains obtaining fastest average access time while minimizing total cost. Hard drives serve as scratch partitions when physical RAM runs low. A system with two gigabytes of RAM might add one gigabyte page file for three gigabytes total availability. Swapping portions back into RAM occurs when previously stored information is needed again. Excessive use results in thrashing that hampers overall system performance. Hard drives are far slower than RAM causing significant delays. Intel summarized causes for slowing improvements in a 2005 document. Chip geometries shrink and clock frequencies rise leading to transistor leakage current. This creates excess power consumption and heat issues. RC delays in signal transmission grow as feature sizes shrink further. Resistance-capacitance bottlenecks impose additional constraints frequency increases cannot address. Multiple levels of caching bridge the widening gap between logic and storage.
The term memory wall describes growing disparity between CPU speed and response time outside the chip. Limited communication bandwidth beyond boundaries explains much of this difference. Constructing memory units of many gibibytes with one-clock-cycle response proves difficult. Modern CPUs often retain mebibyte zero-wait-state cache on the same silicon as cores. Static RAM builds these caches but costs far more than dynamic alternatives. It also consumes significantly more power per bit. The processor-memory performance gap widens over time despite advances. Fast solid state drives increased from four hundred megabits per second via SATA3 in 2012 to seven gigabytes per second via NVMe in 2024. One terabyte of SSD storage costs two hundred dollars while one terabyte of RAM runs into thousands. Fast cheap non-volatile drives replaced functions once performed by RAM. Server farms hold certain data for immediate availability using terabyte-scale SSDs instead. Traditional serial architectures become less efficient as processors accelerate due to von Neumann bottleneck effects. Future solutions may involve three-dimensional integrated circuits reducing distance between logic and memory aspects.
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Common questions
When was the first random-access memory developed?
The Manchester Baby computer successfully ran its first program in June of 1948 using a Williams tube for main memory. This machine stored data as electrically charged spots on the face of a cathode-ray tube that an electron beam could read and write in any order.
What year did magnetic-core memory appear and when did it end?
Magnetic-core memory appeared in 1947 and dominated until the mid-1970s when semiconductor memory displaced it. Engineers constructed arrays of magnetized rings to store data where each ring represented a single bit through its direction of magnetization.
Who invented modern DRAM architecture and what chip came next?
Robert Dennard invented modern DRAM architecture in 1966 with a single transistor per capacitor. Intel released the first commercial DRAM IC chip known as the 1103 in October 1970 which held one kilobit of data on an eight-micrometer process.
How many transistors does static RAM use compared to dynamic RAM?
Static RAM uses six transistors to store each bit while Dynamic RAM relies on a single transistor paired with a capacitor. Static RAM serves as cache memory for CPUs due to its speed whereas Dynamic RAM dominates main memory systems because it is cheaper to produce.
When was the first double data rate SDRAM released by Samsung?
The first commercial double data rate SDRAM arrived in June 1998 from Samsung and held sixty-four megabits of data. Graphics DDR emerged as a form of synchronous graphics RAM also released by Samsung in 1998 utilizing sixteen megabits initially before scaling up.