Random-access memory

• 1. Introduction

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  Random-access memory, the technology most people simply call RAM, is the reason your computer can hold a thought. It is the working space where a machine keeps the code it is running and the data it is actively handling. What makes RAM genuinely unusual is what its name promises: read from it or write to it in any order, and you wait almost exactly the same amount of time no matter where on the chip the data happens to live. That is a stark contrast to older storage media like magnetic tape, where reading something near one end while you are positioned near the other means waiting for the tape to wind across. RAM does not make you wait like that. The story of how this property came to exist stretches from cathode-ray tubes at the University of Manchester in the 1940s, through a lone inventor at IBM in the 1960s, to the Samsung factory floor in the 1990s. Along the way, the device shrank from a cabinet-sized machine to a chip the size of a thumbnail, and it pulled the entire computing industry with it.

• 2. Before the Chip

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  On the 21st of June, 1948, a machine called the Manchester Baby successfully ran a program, and the device that made this possible was not conventional logic. The Baby relied on a Williams tube, a cathode-ray tube repurposed to store data as electrically charged spots on its glass face. Because the electron beam could aim at any spot in any order, the device was genuinely random-access. Capacity was a few hundred to around a thousand bits, which sounds trivial today, but the Williams tube was smaller, faster, and more power-efficient than the only real alternative at the time: latches built from vacuum tubes. Crucially, the Baby was not designed to test a computer concept. It was built to test whether the Williams tube memory was reliable enough to trust.

  Magnetic-core memory arrived in 1947 and lasted as the dominant storage technology until the early 1970s. It relied on an array of magnetized rings, each storing a single bit depending on the direction of its magnetization. Every ring had address wires threaded through it, which meant any location in the array could be selected in any sequence. The approach worked, and it scaled well enough to become the standard form of computer memory for nearly three decades. Before integrated read-only memory circuits existed, permanent random-access storage was often built from diode matrices driven by address decoders, or from specially wound core rope memory. These were the building blocks available to engineers before the transistor changed everything.

• 3. The MOS Revolution

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  In 1957, Frosch and Derick manufactured the first silicon dioxide field-effect transistors at Bell Labs. Three years later, a Bell Labs team demonstrated a working MOSFET. These two achievements set off a chain reaction. John Schmidt at Fairchild Semiconductor developed MOS memory in 1964, producing a technology that was not only faster than magnetic core but also cheaper and less hungry for power. Federico Faggin then advanced the field further at Fairchild in 1968 by developing silicon-gate MOS integrated circuit technology, which made it practical to manufacture MOS memory chips at scale. By the early 1970s, MOS memory had displaced magnetic core as the dominant technology.

  Static RAM arrived on a parallel track. Robert H. Norman at Fairchild invented integrated bipolar static random-access memory in 1963. John Schmidt followed the next year with MOS SRAM at the same company. The catch with SRAM was its cost: each bit of data required six MOS transistors to store. IBM began commercial use of SRAM in 1965 when it introduced the SP95 memory chip for the System/360 Model 95. SRAM is still used today, but almost exclusively as cache memory inside CPUs, where its speed justifies its expense.

• 4. Robert Dennard's Single Transistor

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  In 1966, Robert Dennard was working at IBM examining MOS technology when he found that a MOS transistor could control whether a charge was written to a MOS capacitor. Storing that charge, or the absence of it, could represent a 1 or a 0. This observation led directly to modern DRAM architecture, in which a single MOS transistor pairs with a single capacitor to store one bit. The reduction in transistor count compared to SRAM was enormous. Earlier latch circuits required four to six transistors per bit; Dennard's design needed one. In 1967, he filed a patent under IBM for this single-transistor DRAM memory cell.

  The first commercial DRAM chip to reach the market was the Intel 1103, manufactured on an 8-micrometer MOS process with a capacity of 1 kilobit, released in October 1970. The design carried a tradeoff that has never gone away: the charge stored in each capacitor leaks away in milliseconds, so the circuit must periodically refresh every cell before the data is lost. This refresh process costs power and complexity, but the density and price advantages were decisive. Toshiba had already explored a related concept earlier, with its Toscal BC-1411 electronic calculator in 1965 using capacitor bipolar DRAM to store 180 bits on discrete memory cells built from germanium bipolar transistors and capacitors.

• 5. DRAM Grows Up

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  Early DRAMs ran in step with the CPU clock, but in the mid-1970s the industry moved to asynchronous designs. Then, in 1992, Samsung released the KM48SL2000, a synchronous DRAM chip with a capacity of 16 megabits, signaling a return to clocked operation. Synchronous DRAM let memory and processor coordinate precisely, squeezing out latency. Samsung extended this line further: in June 1998 the company released the first commercial double data rate SDRAM at 64 megabits, and that same year introduced GDDR, a form of synchronous graphics RAM, also as a 16-megabit chip.

  The timeline of DRAM capacity reads like a list of doublings. NEC introduced a 256-kilobit chip in 1980. By 1983, chips at 256 kilobits and even 8 megabits were appearing from various manufacturers. A 64-megabit chip arrived in 1991 from a consortium including Matsushita, Mitsubishi, Fujitsu, and Toshiba. By 1995, NEC had demonstrated a 1-gigabit DRAM. By 1997, NEC pushed to 4 gigabits at a 150-nanometer process. Each generation pushed process geometry down and bit count up, tracking the manufacturing progress happening across the entire semiconductor industry.

• 6. How RAM Actually Works

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  Inside an SRAM chip, each bit is held by a flip-flop circuit, typically implemented with field-effect transistors. The flip-flop holds its state as long as power is present, with no need to refresh. This makes SRAM fast and simple to use, but the six-transistor cell is physically large and expensive to produce. DRAM takes the opposite tradeoff. A single transistor and a single capacitor form each cell. The capacitor holds a high or low charge representing 1 or 0; the transistor acts as a switch letting the control circuitry read or change that charge. Because one cell is far smaller than six, DRAM packs far more bits into the same silicon area, which is why it dominates as main memory in modern computers.

  Addressing is handled through multiplexing and demultiplexing circuitry inside the device. The chip exposes a set of address lines, and each combination of bits on those lines selects a particular set of memory cells. This architecture means RAM devices almost always have capacities that are powers of two. Several memory cells often share one address; a 4-bit-wide chip, for instance, holds four cells per address. When a system needs more addresses than one chip can provide, multiple chips are used together with external multiplexors to divide the address space among them. ECC memory adds a separate layer: special circuitry that uses parity bits or error-correction codes to detect and fix random faults in the stored data.

• 7. The Memory Wall

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  From 1986 to 2000, CPU speed improved at roughly 55 percent per year while off-chip memory response time improved at only about 10 percent annually. Engineers named the resulting gap the memory wall. An Intel document from 2005 outlined the compounding reasons: as chip geometries shrink and clock frequencies rise, transistor leakage current increases, generating excess heat. Memory access times failed to keep pace with rising clock frequencies. For certain workloads, traditional serial processor architectures hit what engineers call the von Neumann bottleneck. And resistance-capacitance delays in signal transmission grow as feature sizes shrink, adding a bottleneck that faster clocks do not address.

  A projection published in a paper titled "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures" forecast a maximum of 12.5 percent average annual CPU performance improvement between 2000 and 2014. The main engineering response to the memory wall has been caching: small amounts of high-speed memory placed close to the processor to hold recently used data. Multiple cache levels have been stacked to manage the widening gap, and modern high-speed computers depend on continuously evolving caching techniques. A 3D integrated circuit approach, which reduces the physical distance between control logic and memory cells, represents another direction. The gap between processor and memory growth can reach as high as 53 percent, according to analyses of the two trajectories.

• 8. RAM Beyond Main Memory

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  Virtual memory extends the apparent size of RAM by designating a portion of a hard drive or SSD as a paging file. A computer with 2 gigabytes of RAM and a 1-gigabyte page file presents the operating system with 3 gigabytes of total addressable memory. When physical RAM fills up, the system swaps portions to disk and reads them back when needed again. Excessive swapping produces a condition called thrashing, which severely degrades performance because hard drives are far slower than RAM.

  Shadow RAM takes the opposite approach: it copies data from a slow ROM chip into faster RAM so the system can respond more quickly to requests that would otherwise reach the chip. The BIOS in typical personal computers often offers an option along these lines. Some virtual private network services have adopted a RAM-only server design where all runtime state, including session metadata and cryptographic material, lives entirely in volatile memory and is erased the moment the server is powered off or rebooted, with the explicit aim of improving security compared to disk-backed designs.

  The competitive landscape around RAM has also shifted. Solid-state drives moved from roughly 400 megabits per second via SATA3 in 2012 to roughly 7 gigabytes per second via NVMe and PCIe by 2024. RAM remains an order of magnitude faster; single-lane DDR5 at 8000 MHz can sustain 128 gigabytes per second. But the price gap matters too: one terabyte of SSD storage was available for around 200 dollars, while one terabyte of RAM would cost thousands, which shapes how engineers decide what to keep in each tier.